Increasing integration of a semiconductor memory device may allow superior performance and a lower price. Since an integration of a semiconductor memory device is a main factor in determining a device price, high integration is beneficial. In a case of two-dimensional or flat semiconductor memory devices, integration is determined mainly by an area which a unit memory cell occupies, so the integration is greatly affected by a level of technique forming a fine pattern. However, since very expensive equipment is needed to obtain a miniature of a pattern, an integration of two-dimensional semiconductor memory device increases, but the increase is still limited.
United States Patent Application Publication No. 2007/0252201 to Kito et al. entitled Nonvolatile semiconductor memory device and manufacturing method thereof discusses a technique of forming memory cells in three dimensions. As discussed therein, a vertical semiconductor pillar is used as an active region and memory cells are three-dimensionally formed. Thus, an area of a semiconductor substrate can be efficiently used and as a result, integration can be greatly increased compared with a conventional two-dimensional semiconductor memory device. Also, since the technique is not based on a method of repeating a step of two dimensionally forming memory cells but the technique forms word lines using a patterning process for defining an active region, a cost per bit can be greatly reduced.